“Quadrature Amplitude Modulation (QAM)” refers to a kind of digital modulation scheme in which symbols are arranged in a lattice form with a specific interval in a signal constellation to determine a magnitude and a phase of a transmission signal, wherein the signal constellation has two axes that represent an in-phase (I) coordinate and a quadrature-phase (Q) coordinate, respectively. A QAM symbol slicer (hereinafter, simply referred to as “QAM slicer”), which serves as an element of a QAM demodulator, extracts an I-component bit sequence and a Q-component bit sequence from a symbol signal that has been QAM-demodulated at a receiving end.
FIG. 1 illustrates a signal constellation used for a conventional 16QAM scheme, which is an example of QAM scheme. In general, as shown therein, a QAM signal constellation includes symbol positions regularly arranged with a specific interval with respect to an I axis and a Q axis such that the coordinates of the symbol positions in the I and Q axes are given as ±(2n−1), wherein n is an integer.
FIG. 2 is a flow chart for illustrating a bit sequence extraction in a conventional QAM slicer used for a conventional QAM having a signal constellation shown in FIG. 1. Referring to FIG. 2, the conventional QAM slicer compares an I or Q component of each symbol signal to a plurality of boundary values of symbol positions in the signal constellation. Although the comparison is performed in a sequential manner in FIG. 2, it can also be performed in a parallel manner. Thereafter, the conventional QAM slicer detects a symbol position closest to the symbol signal, which has been demodulated at the receiving end, in the signal constellation; and extracts two bit sequences that are represented by the symbol signal in the I and Q axes, respectively. Having acquired the bit sequences in this manner, the symbol now can be detected by combining the two bit sequences.
However, the above method of bit sequence extraction by the conventional QAM slicer has a drawback of a high hardware complexity, because, for identifying a single symbol, the I and Q components thereof need to be compared to a plurality of boundary values. Specifically, when the order of QAM modulation increases as 64, 256 and 1024, the number of boundary values to be compared increases greatly, thereby increasing the complexity and aggravating a difficulty in the implementation of the hardware.
In addition to this, the conventional QAM slicer is limited in scalability in that, in accordance with the conventional method, a slicer structure used for a 128QAM scheme cannot be applied to a 256QAM scheme for example.
To solve the above problems, the present invention is to provide an improved symbol slicer and an improved symbol slicing method capable of reducing the hardware complexity while achieving the scalability (i.e., being applicable even if the order of QAM modulation is increased or decreased).